Recording and reproducing apparatus

ABSTRACT

In a recording and reproducing apparatus for recording and reproducing video data, includes: a shuffling memory ( 6 ); a writing means for writing video data into the shuffling memory in accordance with the synchronizing signal and a write reference clock signal in synchronization with the video data; and a reading means for reading out the video data from the shuffling memory in accordance with a synchronizing signal and a stabilized read reference clock which is asynchronous with the write clock signal.

This application is the US national phase of international applicationPCT/JP01/02489 filed 27 Mar. 2001, which designated the US.

TECHNICAL FIELD

The present invention relates to a recording and reproducing apparatus,and in particular relates to a recording and reproducing apparatus forrecording and reproducing a digital video signal.

BACKGROUND ART

With recent development of digital signal processing technologies,apparatus for recording and reproducing high-efficiency coded digitaldata of video signals etc., for example, digital video cassettetape-recorders (referred to hereinafter as DVC), have becomegeneralized.

The present applicant hereof has previously proposed a method ofrecording and reproducing external input video signals such as compositesignals, etc., in a recording and reproducing apparatus.

FIG. 8 shows the embodiment of the previously proposed recording andreproducing apparatus.

In this figure, 1 designates an I/O block(input/output processor), 2 aVSP (Video Signal Processing) block (compressing and expandingprocessor), 3 a DRP (Data Recording Playback) block (recording andreproducing processor), 4 a control block, 5 an input video signalprocessing circuit, 6 a shuffling memory, 7 an orthogonal transformation(data compression coding) circuit, 8 a framing circuit, 9 a PTG memory,10 an encoder, 11 a decoder, 12 an ECC memory, 13 a deframing circuit,14 an inverse orthogonal transformation (data expansion decoding)circuit, 15 an output video signal processing circuit, 16 asynchronization separator circuit, 17 a vertical and horizontalsynchronization separator circuit, 18 an I/O PLL circuit, 19 amultiplexer, 20 an I/O control signal generator circuit, 21 a 13.5 MHzclock generator circuit, 22 4/1 PLL circuit, 23 a frequency divider, 24a frame pulse generation counter, 25 a VSP control signal generatorcircuit, 26 a DRPPLL circuit, 27 a DRP control signal generator circuit,28 an external input control circuit, 29 a phase comparator and 30 adata masking circuit.

This recording and reproducing apparatus is overall configured of I/Oblock 1 as an input/output portion for handling input and output ofvideo signals, VSP block 2 for effecting predetermined processes onvideo data, a DRP block 3 for performing recording and reproducingprocesses for recording and reproducing video data and control block 4for generating clock signals required for blocks 1 to 3 and controllingthe whole apparatus.

Conventionally, during the playback mode in the recording andreproducing apparatus, the frequency of the frame pulse may fluctuatedue to some causes. To deal with cases, a high-precision oscillator suchas a crystal oscillator and the like has been used to provide a stableinternal clock. That is, a stable reproduction is realized by using theframe pulses of a stable frequency generated based on the counts of theinternal clock. However, for reception in the data communication using adigital interface conforming to the IEEE1394 standards (referred tohereinafter as 1394I/F), which has become prevalent recently, the datasynchronously transmitted with the frame pulse from the transmitter sideshould be processed, so that the frame pulse inside the recording andreproducing apparatus as the receiver side needs to be locked with theframe pulse of the transmitter side. In this case, however, thefrequency of the internal frame pulse is expected to fluctuate due tothe phase difference between the frame pulse on the transmitter sideimmediately after the start of reception and the internal frame pulse ordue to jitter of the frame pulse occurring when the source on thetransmitter side is analog and a special playback is performed. Since aPLL circuit is used so as to always keep the number of clock pulseswithin one frame constant, if the frequency of the frame pulsefluctuates, jitter will occur in the pulse width of the system clock,which in turn will cause fluctuations in the monitor output picture orother turbulence. No particular consideration with regard to this pointwas given by the previously proposed recording and reproducingapparatus.

Further, other than there reasons, there is a possibility that the framelength of the frame pulse may vary due to noises etc., and due tosynchronization fluctuations in the circuits. If the number of clockpulses in one frame fluctuates, the synchronism with the video dataloses, causing disturbance in the output video data. The previouslyproposed recording and reproducing apparatus is not the one which givesa particular consideration to this problem.

The object of the present invention is to provide a recording andreproducing apparatus which, even when the synchronism of the framepulse becomes turbulent, can output normal video data and always keepsthe output video data in synchronism and the clock frequency stable.

DISCLOSURE OF INVENTION

In order to solve the above problems, the present invention adopts thefollowing means:—

The first means resides in a recording and reproducing apparatus forrecording and reproducing video data, comprising: a memory; a writingmeans for writing video data into the memory in accordance with thesynchronizing signal and a write reference clock signal insynchronization with the video data; and a reading means for reading outthe video data from the memory in accordance with a synchronizing signaland a stabilized read reference clock asynchronous with the write clock,wherein the memory at least has a capacity of three frames of video dataand is provided with a page management means for managing the framepages of the memory, and the reading means reads the video data, whichhas been written in accordance with the page management means by thewriting means, in accordance with the instructions for double reading ofthe same frame and frame dropping from the page management means.

The second means is characterized in that, in the first means, the pagemanagement means includes: a detecting means for detecting whether theframe length of the frame pulse of video data falls within thedesignated range; and a retaining means for performing control so thatthe writing to the memory and the readout page are retained when thedetecting means detects the fact that the frame length falls out of thepredetermined range.

The third or the fourth means is characterized in that, in the first orthe second means respectively, the memory are used in common forrecording and reproduction. The fifth or the sixth means ischaracterized in that, in the first or the second means, respectively,further comprising a means for recording a compressed stream received byway of an interface (I/F) as being recording by a clock signal obtainedbase on the reference clock signal in synchronism with the receiveddata.

The seventh or the eighth means is characterized in that, in the firstor the second means, respectively at least one of the readout referenceclock signal and the synchronizing signal used by the reading means issupplied from the outside of the recording and reproducing apparatus.

The ninth or the tenth means is a video editing system including amultiple number of recording and reproducing apparatus defined as theabove first or the second means, respectively, and a video editing unitfor editing the video data read out from the memories of the multiplerecording and reproducing apparatus, and is characterized in that thesame reference clock signal and synchronizing signal are used in commonon the side of reading video data from the memories so as to synchronizethe output video picture from each recording and reproducing apparatuswith that from the others.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the configuration of a recording andreproducing apparatus in accordance with the first embodiment of thepresent invention.

FIG. 2 is a diagram showing a memory configuration for one frame in thestandard mode 525/60 system.

FIG. 3 is a diagram for explaining writing and reading processes whenthe period of reading is shorter than that of writing, in the case wherea memory for two frames of video data and a memory for three frames ofvideo data are used.

FIG. 4 is a diagram for explaining writing and reading processes whenthe period of reading is longer than that of writing, in the case wherea memory for two frames of video data and a memory for three frames ofvideo data are used.

FIG. 5 is a block diagram showing the detailed configuration of anexternal input control circuit 28.

FIG. 6 is a chart showing the processing procedures in an external inputcontrol circuit 28.

FIG. 7 is a block diagram showing the configuration of a video editingsystem in accordance with second embodiment of the present invention.

FIG. 8 is a block diagram showing the configuration of a recording andreproducing apparatus according to the prior art.

BEST MODE FOR CARRYING OUT THE INVENTION

To begin with, the first embodiment of the present invention will bedescribed with reference to FIGS. 1 through 6.

FIG. 1 is a block diagram showing the configuration of a recording andreproducing apparatus in accordance with the present embodiment. In thisfigure, 31 designates a 1394I/F processing circuit and 32 designates amultiplexer. Other configurations correspond to those allotted with thesame reference numerals as in FIG. 8 so that description is omitted.

In the present invention, in order to solve the above problems, writingof video data to and reading of it from shuffling memory 6 areasynchronous to each other. In this case, there occurs the problem thatthe data of one frame will mix with that of an adjacent frame, so thatthe method of solving this problem will be first explained.

First, explanation will be made on shuffling of video data. Generally,an orthogonal transformation is performed in order to compress andrecord video data. To achieve this, in order to reduce variations in theamount of information and improve the compression efficiency, shuffling(rearrangement of video data) is performed. On the contrary, when videodata is reproduced, after expansion and inverse orthogonaltransformation, deshuffling (rearrangement of video data in the originalorder) is performed. These shuffling and deshuffling are as a wholereferred to hereinbelow as shuffling process.

In order to simply effect the aforementioned shuffling process, a method(bank method) is used wherein, with two memories each capable of storingone frame of video data provided, data is written into one of them whilethe previous frame data is being read from the other in the orderdifferent from that when the data was written in. However,conventionally the memory were high in price and the memory for twoframes needed for the above bank method was too large in capacity andthis method presented poor cost performance. To solve this problem, ashuffling process using a memory for one frame was used.

Next, with reference to FIG. 2 description will be made on the method ofa shuffling process using a memory for one frame.

FIG. 2 is a diagram showing a memory configuration for one frame in thestandard mode 525/60 system. In this figure, 51 designates a Y-signalDCT block, 52 a Cr-signal DCT block, 53 a Cb-signal DCT block, 54 amacro block, 55 a super block.

First, writing to the memory is performed by the smallest units, calledDCT blocks, each made up of eight samplings in the horizontal directionand eight samplings in the vertical direction. Six DCT blocks, i.e.,four Y-signal DCT block 51, one Cr-signal DCT block 52 and one Cb-signalDCT block 53 are grouped together to form one macro block 54. Further,twenty-seven macro blocks 54 are grouped into one super block 55.Written first is the super block 55 with hatching in the drawing. Thatis, Y-signal OCT blocks 51, namely Y0 to Y3, Cr-signal DCT block 52 andCb-signal DCT block 53 are written in order mentioned in units of macroblock 54. When five super blocks 55 each having 0 to 26 macro blocks 54have been written, the position of writing moves down to the super block55 in the next row and starts therefrom.

Next, retrieval is performed by reading the data in the first field, 240alternate, horizontal lines and then reading the data in the secondfield, similarly 240 alternate, horizontal lines. The data of the nextframe is written into the super block 55 from which the current data hasbeen read out. Thus, the data is successively written into the blocksfrom which the current data has been read out, to thereby realize theshuffling process with a memory for one frame.

Next, the phenomenon of mixture of one frame of data with an adjacentframe of data in the shuffling processing using a memory for one framewill be described.

When the period of reading is shorter than that of writing, writinggradually fails to keep up with the pace of reading so that data is readout from the super blocks 55 from which writing has yet to be done, thusdata having the data from the previous frame mixed therein is read out.When the period of reading is longer than that of writing, readinggradually fails to keep up with the pace of writing so that data of thenext frame is written into the super blocks 55 from which reading hasyet to be done, thus data having the data for the next frame mixedtherein is read out.

Thus, in the case where a shuffling process is performed using thememory for one frame, if the period of writing and that of readingdiffer from each other, data mixture of adjacent frames occurs. Further,since the rule of address rounding of writing/reading breaks down, thereis a possibility that restoration cannot be obtained unless addressrounding is reset, posing difficulties in using this method.

However, because of recent price reduction due to development ofmemories into large capacities and mass production, if an externalmemory is used, a multipurpose memory has become advantageous in costover a dedicated memory for one frame. Use of a 16 Mbit DRAM makes itpossible to provide memory space for three frames even if the standardmode 625/50 system, needing the largest amount of data for one frame(4.75 Mbits),is used. As a result, it becomes possible to use theaforementioned bank method. Next, a comparison will be made between aprocess of shuffling based on the bank scheme using memory for twoframes and that using memory for three frames, when the period ofwriting and that of reading differ from each other.

Referring first to FIG. 3, the case where the period of reading isshorter than that of writing will be described.

FIG. 3(a) shows the case using memory for two frames and FIG. 3(b) showsthe case using memory for three frames. X in the drawings indicates thepoint (the ninth super block in the standard mode 525/60 system) atwhich a sufficient enough amount of data has been written in to startreading while shuffling and reading is performed for the data which hasbeen written beyond the position X. Y in the drawings indicates the endpoint of reading and if writing starts before this point, the data willbecome mixed up. It is also assumed that the first frame of the memoryis A, the second frame is B and the third frame is C.

In FIG. 3(a), since A1 would be read out earlier before the point X atwhich writing of A1 is finished, B0 is read twice. Since writing of B1starts before the point Y at which reading of B0 is finished, the readout data is the mixture of B0 and B1. Then, since reading of A1 isperformed but writing of A2 starts before the point Y at which readingA1 is finished, the read out data is the mixture of A1 and A2.Similarly, for reading of B1, the read out data is the mixture of B1 andB2, and for reading of A2, the read out data is the mixture of A2 andA3. Then, for reading of B2, normal reading free from data mixture canbe restored since next writing of B3 does not start by the point Y atwhich reading of B is finished.

In FIG. 3(b), since C0 would be read out earlier before the point X atwhich writing of C0 is finished, B0 is read twice. Since writing of A1starts after the end of writing of C0, the second reading of B0 isperformed normally without any data mixture, and no mixture of data willoccur thereafter.

Therefore, when shuffling is performed using the memory for two frames,mixed up data is read out from the frame during the period in whichreading and writing overlap. Depending upon the phase difference betweenthe period of reading and the period of writing, mixed data portions andnormal data portions appear periodically. It should be noted that, inthis case, a time lag equivalent to two frames exists within the data inthe mixed data portion. When shuffling is performed using the memory forthree frames, no data mixture will occur by reading appropriate datatwice.

Referring first to FIG. 4, the case where the period of reading islonger than that of writing will be described.

FIG. 4(a) shows the case using memory for two frames and FIG. 4(b) showsthe case using memory for three frames. X in the drawings indicates thepoint (the ninth super block in the standard mode 525/60 system) atwhich a sufficient enough amount of data has been written in to startreading while shuffling. Reading is performed for the data which hasbeen written beyond the position X. Y in the drawings indicates the endpoint of reading and if writing starts before this point, the data willbecome mixed up. It is also assumed that the first frame of the memoryis A, the second frame is B and the third frame is C.

In FIG. 4(a), since writing of B1 starts before the point Y at whichreading of B0 is finished, the read out data is the mixture of B0 andB1. Then, since reading of A1 is performed but writing of A2 startsbefore the point Y, the read out data is the mixture of A1 and A2.Similarly, for reading of B1, the read out data is the mixture of B1 andB2, and for reading of A2, the read out data is the mixture of A2 andA3. For the next reading, since the start point of reading has passed bythe point X at which writing of A3 is finished, A3 is read out withoutreading B2, whereby normal reading free from data mixture is restored.

In FIG. 4(b), after reading, of B1, A2 is read out without reading C1since the start point of reading has passed the point X at which writingof A2 is finished, whereby data free from data mixture can be read outnormally.

Therefore, when shuffling is performed using the memory for two frames,mixed up data is read out from the frame during the period in whichreading and writing overlap. Depending upon the phase difference betweenthe period of reading and the period of writing, mixed data portions andnormal data portions appear periodically. It should be noted that, inthis case, a time lag equivalent to two frames exists within the data inthe mixed data portion. When shuffling is performed using the memory forthree frames, no data mixture will occur by dropping appropriate data.

As described above, when writing to and reading from the shufflingmemory are asynchronous, use of memory for three frames makes itpossible to perform a shuffling process without any mixture of data.

Also in the aforementioned technology proposed by the present applicant,when an external input video signal such as a composite signal, etc., isrecorded, writing the video data into the shuffling memory and readingit therefrom are asynchronous. Since this configuration also uses memoryfor three frames for the same reason as above, the memory for threeframes can be used in common for recording and reproduction.

Next, recording and reproduction of the recording and reproducingapparatus of the present embodiment using shuffling memory 6 for threeframes will be described with reference to FIG. 1.

First, the recording operation of a composite signal, for example, inthis recording and reproducing apparatus will be described.

To begin with, in control block 4, a synchronizing signal is extractedat synchronization separator circuit 16 from the input composite signaland supplied to vertical and horizontal synchronization separatorcircuit 17. In vertical and horizontal synchronization separator circuit17, the synchronizing signal is separated into the verticalsynchronizing signal and horizontal synchronizing signal. I/OPLL circuit18, using the horizontal synchronizing signal as a reference signal,forms the 13.5 MHz clock signal which is recommended by theInternational Telecommunication Union (ITU-R). This clock signal issupplied to I/O control signal generator circuit 20 via multiplexer 19.In I/O control signal generator circuit 20, an I/O control signal isformed and supplied along with the 13.5 MHz clock signal to I/O block 1.

The horizontal synchronizing signal is used in external output controlcircuit 28 as a reference for generation of a frame pulse as an externalinput synchronizing signal when the frame length of the video signal isstandard. When the frame length of the video signal is of a non-standardfrequency, an internal free-running synchronizing signal from afree-running counter is used as a reference to generate a frame pulse.The generated frame pulse is supplied to phase comparator 29 viamultiplexer 32.

In 13.5 MHz clock generator circuit 21, a clock signal of 13.5 MHz isformed and supplied to 4/1PLL circuit 22 and DRPPLL circuit 26. In4/1PLL circuit 22, the 13.5 MHz clock signal is multiplied by 4 so as tocreate a 54 MHz clock signal and this is supplied to frequency divider23. In frequency divider 23, the 54 MHz clock signal is divided by 3 soas to create a 18 MHz clock signal and this is supplied to FP counter 24and VSP control signal generator circuit 25. In FP counter 24, a framepulse is generated based on the counts of the 18 MHz clock signal, andis supplied to VSP control signal generator circuit 25, phase comparator29 and external input control circuit 28. In phase comparator 29, theframe pulse from FP counter 24 and the reference frame pulse input viamultiplexer 32 from external input control circuit 28 are compared. Theresult is supplied to 13.5 MHz clock generator circuit 21 so as toperform control the signals into phase. In VSP control signal generatorcircuit 25, the 18 MHz clock signal from frequency divider 23 and a VSPcontrol signal generated based on the frame pulse from FP counter 24 aresupplied along with the 18 MHz clock signal to VSP block 2. In externalinput control circuit 28, a page control signal for shuffling memory 6and a masking signal are generated and supplied to VSP block 2.

In DRPPLL circuit 26, the 13.5 MHz clock signal from 13.5 MHz clockgenerator circuit 21 is multiplied by 31/10 to form a 41.85 MHz clocksignal, which is supplied to DRP control signal generator circuit 27. InDRP control signal generator circuit 27, based on the 41.85 MHz clocksignal, a DRP control signal is generated, which is supplied togetherwith the 41.85 MHz clock signal to DRP block 3.

Next, in I/O block 1, the input composite signal is sampled anddigitized by input video signal processing circuit 5 and further shapedinto luminance data Y and chrominance data C. These signals are thenwritten into shuffling memory 6 based on the 13.5 MHz clock signalsupplied from control block 4 in accordance with the page managementfrom external input control circuit 28.

In VSP block 2, based on the 18 MHz clock signal supplied from controlblock 4, the video data is read out from shuffling memory 6 inaccordance with the page management from external input control circuit28. The readout data is masked in data masking circuit 30 in accordancewith the masking signal from external input control circuit 28. Then thedata is data compressed through orthogonal transformation circuit 7 andshaped into video data of one picture frame by framing circuit 8, whichis written into PTG memory 9 and added with the parity.

In DRP block 3, the video data is read out from PTG memory 9 based onthe 41.85 MHz clock signal supplied from control block 4 and subjectedto predetermined coding processes by encoder 10 and output to therecording head (not shown).

Next, the playback operation of this recording and reproducing apparatuswill be described.

First, in control block 4 the 13.5 MHz clock signal generated from 13.5MHz clock generator circuit 21 is multiplied by 31/10 in DRPLL circuit26 to form a 41.85 MHz clock signal, which is supplied to DRP controlsignal generator circuit 27. In DRP control signal generator circuit 27,based on the 41.85 MHz clock signal, a DRP control signal is generatedand supplied together with the 41.85 MHz clock signal to DRP block 3. InDRP control signal generator circuit 27, the capstan speed is controlledbased on the pilot signal supplied from the reproducing head (not show)via decoder 11 and recorded on the tape. That is, this allows theplayback head to trace the recording track exactly, hence, it ispossible to reproduce the video data correctly.

The 13.5 MHz clock signal generated from 13.5 MHz clock generatorcircuit 21 is supplied to 4/1PLL circuit 22, wherein the signal ismultiplied by 4 so that a 54 MHz clock signal is generated and suppliedto frequency divider 23. In frequency divider 23, the 54 MHz clock isdivided by 3 to generate a 18 MHz clock signal, which is supplied to FPto counter 24 and VSP control signal generator circuit 25. In FP counter24, a frame pulse, based on the counts of the 18 MHz clock signal, isgenerated and supplied to VSP control signal generator circuit 25. InVSP control signal generator circuit 25, the 18 MHz clock signal fromfrequency divider 23 and the VSP control signal generated based on theframe pulse from FP counter 24 are supplied together with the 18 MHzclock signal to VSP block 2.

In frequency divider 23, the 54 MHz clock signal is divided by 4 into a13.5 MHz clock signal, which is supplied via multiplexer 19 to the I/Ocontrol signal generator circuit. In the I/O control signal generatorcircuit, I/O control signal is formed and supplied together with 13.5MHz clock signal to I/O block 1.

In DRP block 3, the video data reproduced by the playback head (notshown) is supplied to decoder 11, where the data is subjected to thepredetermined decoding process, and the decoded data is written into ECCmemory 12 based on the 41.85 MHz clock signal from control block 4whilst being error-corrected.

In VSP block 2, the video data is read out from ECC memory 12 based onthe 18 MHz clock signal supplied from control block 4, and is suppliedvia deframing circuit 13 to inverse orthogonal transformation circuit14, where the data is subjected to the inverse orthogonal transformationbased on the VSP control signal, and is written based on the 18 MHzclock signal into shuffling memory 6 so that one frame of video datawill be formed.

In I/O block 1, the video data is read out from shuffling memory 6 basedon the 13.5 MHz clock signal supplied from control block 4 and istransformed into the composite data through output video signalprocessing circuit 15 based on I/O control signal whilst being convertedinto analog form and is output outside.

Next, description will be made on the case where monitor output of thevideo data received in the data communications using a 1394I/F isperformed in this recording and reproducing apparatus, in accordancewith the standard frequency composite signal which is input externally.

First, in phase comparator 29, the 1394I/F transmission side frame pulsesupplied via 1394I/F processing circuit 31 is supplied throughmultiplexer 32 and is compared with the frame pulse from FP counter 24.The result is supplied to 13.5 MHz clock signal generator circuit 21 soas to perform control the signals into phase.

Further, the synchronizing signal is extracted from composite signalinput from the Video-In by synchronization separator circuit 16 and issupplied to vertical and horizontal synchronization separator circuit17. In vertical and horizontal synchronization separator circuit 17, thesynchronizing signal is separated into the vertical synchronizing signaland horizontal synchronizing signal. I/OPLL circuit 18, using thehorizontal synchronizing signal as a reference signal, forms the 13.5MHz clock signal, which is recommended by the InternationalTelecommunication Union (ITU-R). This signal is supplied to I/O controlsignal generator circuit 20 via multiplexer 19. In I/O control signalgenerator circuit 20, an I/O control signal is formed and supplied alongwith the 13.5 MHz clock signal to I/O block 1.

In VSP block 2, the input 1394I/F received data is processed through1394I/F processing circuit 31 based on the 18 MHz clock signal suppliedfrom control block 4 and then the data is temporarily written into ECCmemory 12. Thereafter, the video data is read out in accordance with theVSP control signal. The data passes through deframing circuit 13 andthen is subjected to the inverse orthogonal transformation by inverseorthogonal transformation circuit 14. Then the data is written based onthe 18 MHz clock signal into shuffling memory 6 in accordance with thepage management by external input control circuit 28 so that video dataof one picture frame will be formed.

In I/O block 1, based on the vertical synchronizing signal supplied fromvertical and horizontal synchronization separator circuit 17, the videodata is readout, in synchronism with the 13.5 MHz clock signal suppliedfrom control block 4, from shuffling memory 6 in accordance with thepage management from external input control circuit 28, the data isshaped by output video signal processing circuit 15 into the compositedata based on the I/O control signal whilst being converted into analogform and output outside.

In this operation, since writing to, based on the 18 MHz clock signal,and reading from, based on the 13 MHz clock signal, the shuffling memoryare asynchronous, there occur double readings of the same frame and/orframe drops because of the difference between the period of writing andthe period of reading as stated above. However, in the case where the1394I/F received data is recorded onto the tape whilst being monitordisplayed, even though double readings of the same frame and/or framedrops occur on the monitor output side, correct data free from doublereadings of the same frame and frame drops can be recorded on the tapesince the 41.85 MHz clock signal supplied to DRP block 3 is locked withthe 13.5 MHz clock signal from 13.5 MHz clock generator circuit 21,which is based on the 18 MHz clock signal for preparing the frame pulse,hence will never become out of phase.

In FIG. 1, the 13.5 MHz clock signal, being locked with the horizontalsynchronizing signal from the external input composite signal of thestandard frequency, is used as an example as the reference clock forreading the data from shuffling memory 6. However, other than this, useof a crystal oscillator of 13.5 MHz, generation of 13.5 MHz clock signalbased on the burst lock of the external input composite signal and othermethods also make it possible to provide a 13.5 MHz clock signal enoughprecise and stable to achieve stable monitor video output.

Next, with reference to FIGS. 5 and 6, external input control circuit 28will be described.

FIG. 5 is a block diagram showing the detailed configuration of externalinput control circuit 28.

In this figure, 41 designates a frame length determination circuit, 42 areference page generator circuit and 43 a multiplexer.

FIG. 6 is a chart showing the processing procedures in external inputcontrol circuit 28.

When the frame length of the frame pulse fluctuates due to noises etc.,and due to fluctuations of synchronism in the circuits, page managementof shuffling memory 6 is performed as follows. It should be noted thatjitter of the frame pulse at the time of signal reception and the likein the 1394I/F communication does not cause frame length variationssince the clock speed can be kept constant by PLL circuit.

Frame length determination circuit 41 detects the start of a framereferring to the leading edge of the incoming frame pulse and determinesthe previous frame length. If the frame length is longer than thepredetermined length, or if it is shorter than the predetermined length,an error flag is set. Based on this error flag, reference page generatorcircuit 42 performs page management of shuffling memory 6. First, at thetime a frame starts, the page is defined. Then, only when the previousdetermination of the frame length does not result in error, thereference page is updated. If the determination results in error, noreference page will be updated and the current reference page is kept.This reference page is controlled to be output by multiplexer 43switching it from the reference page on the recording side. Based onthis reference page, the writing page is set at the leading end of theframe pulse by adding one to the reference page while the value of thereference page as is set for the readout page at the leading end of theexternal input synchronization.

In this way, the reference page is updated in synchronization with theframe pulse, and writing is performed in synchronization with the 18 MHzclock signal which is locked with the frame pulse whereas readout isperformed in synchronization with the 13.5 MHz clock signal which isasynchronous with the 18 MHz signal. Therefore, even if the frequency ofthe frame pulse varies, it is possible to provide monitor output of thevideo data free from fluctuations based on the stable 13.5 MHz clocksignal.

When a frame length anomaly has occurred, the writing/readout page willbe kept until the frame length reverts itself to the normal or until oneframe of video data becomes able to be normally written into shufflingmemory 6. Therefore, it is possible to output normal video data only.

Next, the second embodiment of the present invention will be describedwith reference to FIG. 7.

FIG. 7 is a block diagram showing the configuration of a video editingsystem involving a multiple number of recording and reproducingapparatus according to the first embodiment for reading out videosignals from the recording and reproducing apparatus to edit video data.

In this figure, 61 designates a video editing unit, 62, 63 and 64designate, respectively, a recording and reproducing apparatus A,recording and reproducing apparatus B and recording and reproducingapparatus C in accordance with the this embodiment.

First, a composite signal of the standard frequency is output as asynchronizing signal from video editing unit 61 and is supplied torecording and reproducing apparatuses A62, B63 and C64. When theplayback operation is performed in each of recording and reproducingapparatuses A62, B63 and C64, the reproduced video data in synchronismwith the vertical and horizontal synchronizing signal of the compositesignal input from video editing unit 61 is output as a composite signalfrom each apparatus and supplied to video editing unit 61. Since theplayback video data outputs from the recording and reproducingapparatuses A62, B63 and C64 are synchronized, it is possible torelatively easily effect a variety of video editing tasks. For example,when the video data from recording and reproducing apparatus A62 andthat from recording and reproducing apparatus B63 need to be connected,the video data can be switched by frame units, thus enabling smoothconnection. Further, when, for example, composition of the video datafrom recording and reproducing apparatus B63 and that from recording andreproducing apparatus C64 is carried out, it is possible to smoothlyeffect the composite task of the video data since no synchronismadjustment is needed.

Though the above description of the present video editing system wasmade on a case where three recording and reproducing apparatuses areused, the system can be applied to a configuration including at leasttwo.

As described above, in accordance with the invention of the presentembodiment, even if the frequency of the frame pulse fluctuates duringplayback, it is possible to produce a monitor output free fromdisturbance in accordance with the externally input, stablesynchronizing signal and clock signal.

Further, use of the shuffling memory for three frames makes it possibleto avoid mixture of data within one frame, and management of the framepages makes it possible to output a normal video data even if the framelength of the frame pulse fluctuates.

Also in receiving and recording a compressed stream through a 1394I/F,use of the synchronizing signal synchronized with the received data andthe reference clock signal on the recording side makes it possible toperform normal recording regardless of the monitor output even when thefrequency of the received frame pulse is disturbed.

Further, use of at least two sets of recording and reproducing apparatusaccording to the present embodiment and use of the same synchronizingsignal input to each enables output of the playback video data from eachapparatus in synchronism with that of the others.

INDUSTRIAL APPLICABILITY

According to the first through the fourth means of the presentinvention, since a stable readout reference clock signal is used to readout video data from the shuffling memory, it is possible to reproducethe monitor output picture even if jitter arises in the internal framepulse, and furthermore, since a shuffling memory for three frames isused, it is possible to perform reproduction of data without any mixtureof data in each frame. Further, even if the frame pulse fluctuates,management of the frame pages in the shuffling memory for three framesby detecting fluctuations of the frame pulse makes it possible to outputnormal video data, providing improved quality of image when the data isreproduced.

According to the fifth and the sixth means of the present invention,since in receiving and recording of a compressed stream, recording isperformed in synchronism with the clock signal based on the receivedframe pulse and a reference clock signal which is locked with thereceived frame pulse, it is possible to perform normal recording andimprove the quality of the monitor output video picture even if jitterarises in the received frame pulse.

According to the seventh and the eighth means of the present invention,since the video data can be output in synchronism with the inputsynchronizing signal from without, it is possible to use a multiplenumber of the recording and reproducing apparatus and impact the samesynchronizing signal.

According to the ninth and the tenth means of the present invention,since the video data can be output in synchronization with the inputsynchronizing signal from without, use of a multiple number of therecording and reproducing apparatus and imparting the same synchronizingsignal make it possible to synchronize the output video data of eachwith that of the others and hence provide ease of performing videoediting tasks.

1. A recording and reproducing apparatus for recording and reproducingvideo data, comprising: a memory; a writing means for writing video datainto the memory in accordance with a synchronizing signal and a writereference clock signal in synchronization with the video data; and areading means for reading out the video data from the memory inaccordance with a synchronizing signal and a stabilized read referenceclock asynchronous with a write clock, wherein the memory at least has acapacity of three frames of video data and is provided with a pagemanagement means for managing frame pages of the memory, and the readingmeans reads the video data, which has been written in accordance withthe page management means by the writing means, in accordance withinstructions for double reading of the same frame and frame droppingfrom the page management means.
 2. The recording and reproducingapparatus according to claim 1, wherein the page management meansincluded: a detecting means for detecting whether a frame length of aframe pulse of video data falls within a designated range; and aretaining means for performing control so that the writing to the memoryand a readout page are retained when the detecting means detects thatthe frame length falls out of the predetermined range.
 3. The recordingand reproducing apparatus according to claim 1, wherein the memory isused in common for recording and reproducing.
 4. The recording andreproducing apparatus according to claim 2, wherein the memory is usedin common for recording and reproduction.
 5. The recording andreproducing apparatus according to claim 1, further comprising a meansfor recording a compressed stream received by way of an interface (I/F)as being recorded by a clock signal obtained based on the referenceclock signal in synchronism with received data.
 6. The recording andreproducing apparatus according to claim 2, further comprising a meansfor recording a compressed stream received by way of an interface (I/F)as being recorded by a clock signal obtained based on the referenceclock signal in synchronism with the received data.
 7. The recording andreproducing apparatus according to claim 1, wherein at least one of thereadout reference clock signal and the synchronizing signal used by thereading means is supplied from the outside of the recording andreproducing apparatus.
 8. The recording and reproducing apparatusaccording to claim 2, wherein at least one of the readout referenceclock signal and the synchronizing signal used by the reading means issupplied from the outside of the recording and reproducing apparatus. 9.A video editing system including a multiple number of recording andreproducing apparatus according to claim 1 and a video editing unit forediting the video data read out from the memories of the multiplerecording and reproducing apparatus, characterized in that a samereference clock signal and synchronizing signal are used in common onthe side of reading video data from the memories so as to synchronize anoutput video picture from each recording and reproducing apparatus withthat from the others.
 10. A video editing system including a multiplenumber of recording and reproducing apparatus according to claim 2 and avideo editing unit for editing the video data read out from the memoriesof the multiple recording and reproducing apparatus, characterized inthat a same reference clock signal and synchronizing signal are used incommon on the side of reading video data from the memories so as tosynchronize an output video picture from each recording and reproducingapparatus with that from the others.
 11. A recording and reproducingapparatus for recording and reproducing video data, comprising: amemory; a writing means for writing video data into the memory inaccordance with a synchronizing signal and a write reference clocksignal in synchronization with the video data; and a reading means forreading out the video data from the memory in accordance with asynchronizing signal and a stabilized read reference clock asynchronouswith a write clock, wherein the memory at least has a capacity of threeframes of video data and is provided with a page management means formanaging frame pages of the memory, and the reading means reads thevideo data, which has been written in accordance with the pagemanagement means by the writing means, in accordance with instructionsfor double reading of the same frame or frame dropping from the pagemanagement means.
 12. The recording and reproducing apparatus accordingto claim 11, wherein the page management means includes: a detectingmeans for detecting whether a frame length of a frame pulse of videodata falls within a designated range; and a retaining means forperforming control so that the writing to the memory and a readout pageare retained when the detecting means detects that the frame lengthfalls out of the predetermined range.
 13. The recording and reproducingapparatus according to claim 11, wherein the memory is used in commonfor recording and reproducing.
 14. The recording and reproducingapparatus according to claim 12, wherein the memory is used in commonfor recording and reproduction.
 15. The recording and reproducingapparatus according to claim 11, further comprising a means forrecording a compressed stream received by way of an interface (I/F) asbeing recorded by a clock signal obtained based on the reference clocksignal in synchronism with received data.
 16. The recording andreproducing apparatus according to claim 12, further comprising a meansfor recording a compressed stream received by way of an interface (I/F)as being recorded by a clock signal obtained based on the referenceclock signal in synchronism with the received data.
 17. The recordingand reproducing apparatus according to claim 11, wherein at least one ofthe readout reference clock signal and the synchronizing signal used bythe reading means is supplied from the outside of the recording andreproducing apparatus.
 18. The recording and reproducing apparatusaccording to claim 12, wherein at least one of the readout referenceclock signal and the synchronizing signal used by the reading means issupplied from the outside of the recording and reproducing apparatus.19. A video editing system including a multiple number of recording andreproducing apparatus according to claim 11 and a video editing unit forediting the video data read out from the memories of the multiplerecording and reproducing apparatus, wherein a same reference clocksignal and synchronizing signal are used in common on the side ofreading video data from the memories so as to synchronize an outputvideo picture from each recording and reproducing apparatus with thatfrom the others.
 20. A video editing system including a multiple numberof recording and reproducing apparatus according to claim 12 and a videoediting unit for editing the video data read out from the memories ofthe multiple recording and reproducing apparatus, wherein a samereference clock signal and synchronizing signal are used in common onthe side of reading video data from the memories so as to synchronize anoutput video picture from each recording and reproducing apparatus withthat from the others.